The present invention relates to video processing, and in particular, to video decoding using a hybrid buffer.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Video processing may be bandwidth intensive, computationally intensive and storage intensive. The bandwidth requirements are increasing as higher quality video is becoming available via broadcast, download, or from storage media. The computation requirements are increasing as compression is used (to reduce the bandwidth) and as an increasing number of processing formats are developed. The storage requirements are increasing along with the quality of the video, since display devices are accessing more data from the video processors.
For example, in many devices, the processor must remain in the loop when devices are transferring data either to the processor or to the memory.
As another example, in many devices, the processor must spend time to program various configuration registers before data processing can begin, which potentially wastes time.
As a further example, in many devices, the processor must program various configuration registers over a relatively slow bus, which potentially wastes time.
As a still further example, in many devices, a bus can enter an invalid state due to incomplete transactions during a reset operation.
Thus, there is a need for improved systems for video processing.